Many electronic devices have an embedded processor with several types of memory connected through a bus. Usually there are several stages of memory connected to the processor, varying in size and speed.
As is shown in FIG. 1, a typical, prior art version of such an electrical device contains a Central Processing Unit (CPU) 3 for processing and controlling the whole electrical device, a Closely Coupled Memory (CCM) 5 for storing data and/or instructions, an external memory system 8 comprising external memory as well as a related external memory bus controller 13 and which external memory 8 is arranged for storing data and/or instructions. A clock unit 1 receives a master clock signal 2 for generating a main system clock signal 6 for the electrical device, i.e. for the CPU 3, the CCM 5 and the external memory 8. The device comprises an internal memory bus 4 for connecting the CPU 3 with the CCM 5, and an external memory bus 7 for connecting the CCM 5 with the external memory 8.
The memory bus controller 13 is integrated on the chip and is connected to the CPU 3 to receive read and write instructions from CPU 3. After having received a read request from CPU 3, memory bus controller 13 retrieves the requested data from external memory 7 for CCM 5. CCM 5 is arranged to receive that data and to store it at a predetermined memory location where CPU 3 can access it.
The CPU 3, the clock unit 1, the CCM 5 and the memory bus controller 13 are integrated in one single chip 14 (embedded). The CCM 5 is the smallest and fastest type of memory. The CCM 5 is optimized for speed rather than size. As the CCM 5 is integrated into the device, the cost per byte is relatively high. The external memory 8 is connected to the CCM 5 through external memory bus 7. The external memory 8 can be cost optimized for size and is usually slower than the integrated CCM 5. The electrical device is clocked by master clock signal 2. The clock unit 1 converts the master clock signal 2 into a faster version of the master clock signal 2 (e.g. by a Phase Locked Loop) or a slower version of master clock signal 2 (e.g. by a Clock Divider). The input of clock unit 1 is the master clock signal 2 and the output of clock unit 1 is the main system clock signal 6. The main system clock signal 6 clocks the CPU 3, CCM 5, external memory controller 13 and external memory 8.
The power Pccmactive consumed by the CPU 3, CCM 5 and other components on the chip which are active when the device is active consists of two components. One being a static power consumption Pccmstatic and the second one being a dynamic power consumption Pccmdynamic, which is dependent on the speed on which the device is operated. The following formula holds:Pccmactive=Pccmstatic+Pccm(fclock)dynamic  (1)In this formula,
Pccm(fclock)dynamic is a function of fclock:
Pccm(fclock)dynamic=fclock*APdyn(CCM) 
Where:
APdyn(CCM) is a constant with unit [W/Hz],
fclock=frequency of main system clock signal 6 in Hz as received by CCM 5.
From the formula it is clear that minimum power consumption for components in the system which are active when the device is active is achieved when fclock is as low as possible. Therefore, the main system clock signal 6 is designed to be equal to or slower than the master clock signal 2 for the sake of conserving power. By making the main system clock signal 6 slower than the master clock signal 2, the dynamic power consumption of components which are active when the device is active, such as CPU 3 and CCM 5, will be lower than the situation when the main system clock signal 6 is the same as the master clock signal 2. When the CCM 5 is used as a cache memory, the processor 3 will fetch a high percentage of its instructions from CCM 5 over internal memory bus 4 (in the order of 90% or higher) and only few instructions need to be fetched from the external memory 8 over external memory bus 7. In this way, the average bus speed will be close to the speed of internal memory bus 4 as most instructions are fetched from the fast CCM 5. Fetching the remaining instructions from the external memory 8 is relatively slow, but since the number of instructions is limited this has a minor impact on the average bus speed.
The power Pextactive consumed by the external memory 8 while active consists of two components. One being the static power consumption Pextstatic which is always present when the device is active, for example when the device is selected by means of a chip_select signal or chip_enable signal. The second one being the dynamic power consumption Pextdynamic, which is dependent on the speed, i.e. the clock frequency, the device is operated.Pextactive=Pextstatic+Pext(fclock)dynamic  (2)In this formula,
Pext(fclock)dynamic is a function of fclock:
Pext(fclock)dynamic=fclock*APdyn(ext) 
Where:
APdyn(ext) is a constant with unit [W/Hz],
fclock=frequency of main system clock signal 6 in Hz as received by external memory 8.
The total power consumption consumed by the external memory 8 while inactive consists of one component; i.e. the standby power consumption Pextstandby. It is commonly known that the standby power consumption Pextstandby is smaller than the static power consumption Pextstatic.
The total power Pexttotal consumed by the external memory device 8 is equal to the active power consumption Pextactive multiplied by the relative active period Tactive (defined as part per unit time) plus the standby power consumption Pextstandby multiplied by the relative standby period Tstandby (defined as part per unit time). So, Tactive+Tstandby=1, and:
                                                                        Pext                total                            =                            ⁢                                                                    T                    active                                    *                                      (                                                                  Pext                        static                                            +                                                                        Pext                          ⁡                                                      (                                                          f                              clock                                                        )                                                                          dynamic                                                              )                                                  +                                                                                                      ⁢                                                T                  standby                                *                                  (                                      Pext                    standby                                    )                                                                                                        =                            ⁢                                                                    T                    active                                    *                                      (                                                                  Pext                        static                                            +                                                                        f                          clock                                                *                                                  A                                                      Pdyn                            ⁡                                                          (                              ext                              )                                                                                                                                            )                                                  +                                                                                                      ⁢                                                (                                      1                    -                                          T                      active                                                        )                                *                                  (                                      Pext                    standby                                    )                                                                                                        =                            ⁢                                                                    T                    active                                    *                                      (                                                                  Pext                        static                                            +                                                                        f                          clock                                                *                                                  A                                                      Pdyn                            ⁡                                                          (                              ext                              )                                                                                                                          -                                              Pext                        standby                                                              )                                                  +                                                                                                      ⁢                              Pext                satndby                                                                        (        3        )            
Assume the amount of data per time unit retrieved is a linear function of the frequency fclock of the main system clock signal 6 as received by external memory 8, then the relative active period Tactive can be expressed as follows when retrieving N bytes:Tactive=CO*N/fclock  (4)Where C0=constant [HZ]When accessing the external memory 8 we may assume these N bytes can consist of either the following items or a combination of the following items:
A command (write/read/status/ . . . )
An address (which byte or data the command has to operate on)
Data (actual payload)
The access format to the external memory is not limited to the above items.
This means:
                                                                        Pext                total                            =                            ⁢                                                C                  0                                *                                  N                  /                                      f                    clock                                                  *                                                                                                      ⁢                                                (                                                            Pext                      static                                        +                                                                  f                        clock                                            *                                              A                                                  Pdyn                          ⁡                                                      (                            ext                            )                                                                                                                -                                          Pext                      standby                                                        )                                +                                                                                                      ⁢                              Pext                standby                                                                                        =                            ⁢                                                C                  0                                *                N                *                                                                                                      ⁢                                                (                                                                                    Pext                        static                                            /                                              f                        clock                                                              +                                          A                                              Pdyn                        ⁡                                                  (                          ext                          )                                                                                      -                                                                  Pext                        standby                                            /                                              f                        clock                                                                              )                                +                                                                                                      ⁢                              Pext                standby                                                                        (        5        )            Given that Pextstatic, APdyn(ext) and P(ext)standby are constants, the formula can be written as:Pexttotal=C0*N*(C1/fclock+C2)+C3  (6)Where:
C1=Pextstatic−Pextstandby 
C2=APdyn(ext) 
C3=Pextstandby 
From the formula it is clear that minimum power consumption is achieved when fclock is as high as possible, for any given amount of data N per time unit. However, this is in direct conflict with formula (1) which states the minimum power consumption of components in the system which are active when the system is active can be achieved by using a low fclock.